004.38 — Виды компьютеров

Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory Sitian Chen, Yusen Li, Yao Chen, Minwen Deng, Jintao Meng, Amelie Chi Zhou · 2026

Code size reduction by advanced near addressing modes Kajetan Nuernberger, Thomas Roecker, Gergely Fueto, Gabor Spaits, Horst Lehser · 2026

Posture Clip: Sit properly or I wont let you work Arka Majhi, Aparajita Mondal · 2026

DiSC: Resolution-Scalable Acceleration of Diffusion Models by Exploiting Sparsity and Cached Token Reuse with Hash-based Distribution Jieon Yoon, Hangyeol Lee, Jaehoon Heo, Joo-Young Kim · 2026

Mutually Unbiased Bases for Variational Quantum Initialization: Basis-Union Optimality and Adaptive Family Search Abed Semre, Steven Frankel · 2026

Evaluating System-Level Fidelity with Peaked Random Circuits Martin Brieger, Florian Krötz, Minh Chung, Dieter Kranzlmüller · 2026

The Evolution of Digital Twins from Reactive to Agentic Systems Omer San, Adil Rasheed, Eda Bozdemir, Jun Deng · 2026

PoisonCap: Efficient Hierarchical Temporal Safety for CHERI Yuecheng Wang, Jonathan Woodruff, Alfredo Mazzinghi, Peter Rugg, Alexandre Joannou, Samuel W. Stark, Robert N. M. Watson, Simon W. Moore · 2026

Reward-Weighted On-Policy Distillation with an Open Property-Equivalence Verifier for NL-to-SVA Generation Qingyun Zou, Yingze Li, Tianen Liu, Bingsheng He, Weng-Fai Wong · 2026

dSABRE: A SABRE-Style Router for Multi-Core Distributed Quantum Computers Sanjiang Li · 2026

LIDSA: Cognitive Arbitration for Signal-Free Autonomous Intersection Management Abderrahmane Lakas, Mohamed Amine Ferrag, Merouane Debbah · 2026

A Rigid Category of DNA Secondary Structures Andrés Ortiz-Muñoz · 2026

A Hybrid Tucker-LSTM Tensor Network Model for SOC Prediction in Electric Vehicles Han Wang, Ying Wang, Bing Wang · 2026

Embodied Neurocomputation: A Framework for Interfacing Biological Neural Cultures with Scaled Task-Driven Validation Johnson Zhou, Daniel Tanneberg, Forough Habibollahi, Alon Loeffler, Kiaran Lawson, Valentina Baccetti, Kwaku Dad Abu-Bonsrah, Candice Desouza, Finn Doensen, Bradley Watmuff, Daria Kornienko, Azin Azadi, Justin Leigh Bourke, Bernhard Sendhoff, Brett J. Kagan · 2026

Design of 5-Stage Hazard-Free Pipelined Architecture for RISC-V-Based Processor Dakshika Sharma, Ankur Kumar, Naman Garg · 2026

Automatic De-Quantization of Quantum Programs Using Constant Propagation Lian Remme, Alexander Weinert, Andre Waschk, Lukas Burgholzer, Robert Wille · 2026

Which Superconducting Qubit Model is Good Enough? From Effective Two-Level to Circuit-Based Hamiltonians for Pulse-Level Simulation Frej Larssen, Ivy Peng, Stefano Markidis · 2026

Classical State Preparation for Variational Quantum Algorithms via Reinforcement Learning Gino Kwun, Dhanvi Bharadwaj, Gokul Subramanian Ravi · 2026

Cost-Effective Model Evaluation with Meta-Learning Trinh Pham, Viet Huynh, Hongzhi Yin, Quoc Viet Hung Nguyen, Thanh Tam Nguyen · 2026

Jurisdiction over Ubiquitous Copyright Infringements: Should Right-Holders Be Allowed to Sue at Home? Paulius Jurcys, Toshiyuki Kono · 2026

Measurement-Driven Adaptive Low-Overhead Implementation of Multi-Controlled Toffoli Gates Abhoy Kole, Till Schnittka, Rolf Drechsler · 2026

The Hidden Cost of Contextual Sycophancy: an AI Literacy Intervention in Human-AI Collaboration Cansu Koyuturk, Sabrina Guidotti, Dimitri Ognibene · 2026

DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling David Metz, Magnus Själander · 2026

To Overlay or to Customize? Revisiting Architectural Choices in Heterogeneous Systems Xingzhen Chen, Shixin Ji, Zheng Dong, Peipei Zhou · 2026

UniSpike: Accelerating Spiking Neural Networks on Neuromorphic Systems via Eliminating Address Redundancy Qinghui Xing, Zhuo Chen, Xin Du, Ouwen Jin, Ming Zhang, Pan Lv, Ying Li, Shuiguang Deng, Gang Pan · 2026

DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration Xingzhen Chen, Zhuoping Yang, Jinming Zhuang, Shixin Ji, Sarah Schultz, Zheng Dong, Weisong Shi, Peipei Zhou · 2026

Hardware Design Space Exploration of a Selection of NIST Lightweight Cryptography Candidates Mustafa Khairallah · 2021

Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design Hai Lin, Yunsi Fei · 2009

Search Your Block Floating Point Scales! Tanmaey Gupta, Hayden Prairie, Xiaoxia Wu, Reyna Abhyankar, Qingyang Wu, Austin Silveria, Pragaash Ponnusamy, Jue Wang, Ben Athiwaratkun, Leon Song, Tri Dao, Daniel Y. Fu, Chris De Sa · 2026

ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation Zhongkai Yu, Yichen Lin, Chenyang Zhou, Yuwei Zhang, Kun Zhou, Junxia Cui, Haotian Ye, Zhengding Hu, Zaifeng Pan, Ruiyi Wang, Yujie Zhao, Hejia Zhang, Jingbo Shang, Jishen Zhao, Yufei Ding · 2026

A detailed algorithmic study on a reuse-aware, near memory, all-digital Ising machine Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni · 2026

GenAI-Driven Approach to RISC-V Supply Chain Exploration Nenad Petrovic, Andre Schamschurko, Yingjie Xu, Alois Knoll · 2026

TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing Yavuz Selim Tozlu, Anshul Naithani, Huiyang Zhou · 2026

A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture Siddhartha Raman Sundara Raman, Lizy K John, Jaydeep P. Kulkarni · 2026

Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power Traces Oran Hayes, Maria Pantazi-Kypraiou, Athanasios Tziouvaras, George Stamoulis, Anuj Pathania, Shreejith Shanker, George Floros · 2026

VeriCache: Turning Lossy KV Cache into Lossless LLM Inference Jiayi Yao, Samuel Shen, Kuntai Du, Shaoting Feng, Dongjoo Seo, Rui Zhang, Yuyang Huang, Yuhan Liu, Shan Lu, Junchen Jiang · 2026

TuniQ: Autotuning Compilation Passes for Quantum Workloads at Scale for Effectiveness and Efficiency Mohammad Abrarul Hasanat, Jason Ludmir, Tirthak Patel, Rohan Basu Roy · 2026

Performance of QUBO-Formulated MIMO Detection Under Hardware Precision Constraints Seyedkhashayar Hashemi, Elisabetta Valiante, Ignacio Rozada, Moslem Noori · 2026

A Fast and Energy-Efficient Latch-Based Memristive Analog Content-Addressable Memory Paul-Philipp Manea, Aishwarya Natarajan, Jim Ignowski, John Paul Strachan, Luca Buonanno · 2026

When Noisy Quantum Order Finding Remains Recoverable for Shor's Algorithm Qingxin Yang, Stefano Markidis · 2026

Performance Gains in Quantum SAT Solvers Using ESOP Encoding Majd Assaad, Abhoy Kole, Rolf Drechsler · 2026

BIDO: A Biometric Identity Online Authentication Framework Aditya Mithra, Sibi Chakkaravarthy S, Srinivas Kankanala · 2026

Quantum Genetic Optimization for Negative Selection Algorithms in Anomaly Detection Giancarlo P. Gamberi, Calebe P. Bianchini · 2026

Whole-Blood Boundary Analysis of BioFET-Based ctDNA Detection for Intravascular Sensing in Intrabody Nanonetworks Ida Kleger-Rudomin, Filip Lemic, Sergi Abadal, Eduard Alarcon, Ethungshan Shitiri · 2026

Stencil Computations on Tenstorrent Wormhole Lorenzo Piarulli, Daniele De Sensi · 2026

Per-Phase Fidelity Attribution for Quantum Compilers using HBR Decomposition Chandrachud Pati, Yogesh Simmhan · 2026

LCGuard: Latent Communication Guard for Safe KV Sharing in Multi-Agent Systems Sadia Asif, Mohammad Mohammadi Amiri, Momin Abbas, Prasanna Sattigeri, Karthikeyan Natesan Ramamurthy · 2026

Non-Monotonic Latency in Apple MPS Decoding: KV Cache Interactions and Execution Regimes Willy Fitra Hendria · 2026

31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Di Pang, Songchen Ma, Xijie Huang, Shih-Yang Liu, Dong Zhang, Zhichao Lu, Luhong Liang, Chi-Ying Tsui, Fengbin Tu, Liang Zhao, Kwang-Ting Cheng · 2026

CompPow: A Case for Component-level GPU Power Management Shaizeen Aga, Mohamed Assem Ibrahim · 2026

Emerging memory technologies at room/cryogenic temperature Siddhartha Raman Sundara Raman · 2026

NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing Cheng Zou, Shuo Yang, Chen Nie, Yu Zou, Yu He, Chao Jiang, Limin Xiao, Weifeng Zhang, Zhezhi He · 2026

ORBIS: Output-Guided Token Reduction with Distribution-Aware Matching for Video Diffusion Acceleration Hangyeol Lee, Joo-Young Kim · 2026

Coarse-granularity 3D Processor Design Yuan Xie, Jishen Zhao · 2015

An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture James Goodman, Anantha Chandrakasan · 2000

Multiprocessor and Many-Core Protections Jakub Szefer · 2019

Low Resource-Cost Depthwise Separable Convolutional Co-Processor Architecture : Embedded Co-Processor Design Huangxu Chen, Mingjian Zhao · 2023

ELSA: An ELastic SNN Inference Architecture for Efficient Neuromorphic Computing Kang You, Chen Nie, Lee Jun Yan, Ziling Wei, Cheng Zou, Zekai Xu, Yu Feng, Honglan Jiang, Zhezhi He · 2026

Towards transistor-based quantum computing Y. -D. Liu, X. Xu, Q. -R. Wang, D. -S. Wang · 2026

Cloud-Native Operation of Roadside Infrastructure Enabling Demand-Driven Collective Perception via V2X Lukas Zanger, Fabian Thomsen, Guido Linden, Jean-Pierre Busch, Lennart Reiher, Lutz Eckstein · 2026

Supporting Dynamic Control-Flow Execution for Runtime Reconfigurable Processors Hassan Nassar, Rafik Youssef, Lars Bauer, Jörg Henkel · 2026

Processor and Instruction-Set Architectures Sajjan G. Shiva · 2025

Execution Envelopes: A Shared Admission Contract for Backend AI Execution Requests Krti Tallam · 2026

Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation Chih-Hua Ke · 2026

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu · 2026

Low-Complexity Beamspace Channel Denoiser for mmWave Massive MIMO with Low-Resolution ADCs Hanyoung Park, Eunho Kim, Ji-Woong Choi · 2026

HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators Ayushi Agarwal, Anannya Mathur, Preeti Ranjan Panda · 2026

Inverse Design of Metasurface based Absorbers using Physics Guided Conditional Diffusion Models Vineetha Joy, Jamshed Palai, Satwik Sahoo, Anshuman Kumar, Amit Sethi, Hema Singh · 2026

Verification Challenges in Configurable Processor Design with ASIP Meister Masaharu Imai, Akira Kitajima · 2005

Reconfigurable Computing Challenge: Real-Time Graph Neural Networks for Online Event Selection in Big Science Marc Neu, Frank Baptist, Thomas Lobmaier, Fabio Papagno, Torben Ferber, Jürgen Becker · 2026

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri · 2026

TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments Yue Guan, Hongtao Yu, Peng Chen, Daohang Shi, Karthik Manivannan, Nicholas J Riasanovsky, Manman Ren, Lei Wang, Shane Nay, Partha Kanuparthy, Zaifeng Pan, Zhengding Hu, Yufei Ding · 2026

Sieve: Dynamic Expert-Aware PIM Acceleration for Evolving Mixture-of-Experts Models Jungwoo Kim, Rubens Lacouture, Genghan Zhang, Gina Sohn, Qizheng Zhang, Swapnil Gandhi, Christos Kozyrakis, Kunle Olukotun · 2026

Quantum Annealing: Optimisation, Sampling, and Many-Body Dynamics Steven Abel, Andrei Constantin, Luca A. Nutricati · 2026

Genetic Information as a "Chord" of Chemical Oscillations: Emergence of Catalyst-RNA Systems Driven by Superposed Rhythms Takeshi Ishida · 2026

A3D: Agentic AI flow for autonomous Accelerator Design Abinand Nallathambi, Christopher Knight, Shantanu Ganguly, Wilfried Haensch, Anand Raghunathan · 2026

Hardware Root of Trust Jakub Szefer · 2019

A Simple Computer: Hardware Design · 2007

Post-Moore Technologies for Plasma Simulation: A Community Roadmap Luca Pennati, Erik M. Åsgrim, Jeremy J. Williams, Stefan Costea, David Tskhakaya, Leon Kos, Ales Podolnik, Yi Ju, Tapish Narwal, Julian Lenz, Michael Bussmann, Urs Ganse, Minna Palmroth, Kallia Chronaki, Vassilis Papaefstathiou, Etienne Renault, Felix Jung, Martin Schulz, Valentin Seitz, Marta Garcia-Gasulla, Filippo Mantovani, Frank Jenko, Erwin Laure, Stefano Markidis · 2026

Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling Yinrong Li, Zexin Fu, Yichao Zhang, Germain Haugou, Chi Zhang, Marco Bertuletti, Bowen Wang, Luca Benini · 2026

AccelSync: Verifying Synchronization Coverage in Accelerator Pipeline Programs Hangcheng An, Rui Wang, Depei Qian · 2026

FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors Logashree Venkatasubramanian, Zishen Wan, Viveck Cadambe · 2026

An adaptive hardware machine architecture and compiler for dynamic processor reconfiguration P.M. Athanas, H.F. Silverman · 2024

Vector and Multiple-Processor Machines · 2017

Processor and Instruction-Set Architectures · 2013

Dual-Execution Processor Architecture for Embedded Computing Abderazek Ben Abdallah · 2010

Adaptive Clifford+T Decomposition of Large Toffoli Gates with One Clean Ancilla Abhoy Kole, Majd Assaad, Till Schnittka, Rolf Drechsler · 2026

Efficient Implementation of an Adaptive Transformer Accelerator for Massive MIMO Outdoor Localization Ilayda Yaman, Sijia Cheng, Ove Edfors, Liang Liu · 2026

Memristor Technologies for Dynamic Vision Sensors: A Critical Assessment and Research Roadmap Mohamad Yazan Sadoun, Edris Zaman Farsa, Sarah Sharif, Yaser Mike Banad · 2026

■ HARDWARE ARCHITECTURE · 2016

IBM AS/400 processor architecture and design methodology Q.G. Schmierer, A.H. Wottreng · 2024

Power Efficient Processor Architecture and The Cell Processor H.P. Hofstee · 2024

A Case Study: Formal Verification of Processor Critical Properties Emmanuel Zarpas · 2005

An Efficient Hardware Architecture Design of EEMD Processor for Electrocardiography Signal I-Wei Chen, Shang-Yi Chuang, Wen-Lun Wu, Wai-Chi Fang · 2018

Teaching Computer Architecture through an Integrated Top-Down RISC-V Processor Design Approach Guilherme Esmeraldo, Edson Lisboa, Victor Medeiros, Edna Barros · 2025

Introduction Vahid Lari · 2016

Abc's Of Processor Design: Introductory Computer Architecture Using The Lis 4 Ravi Pendse, Everett L. Johnson · 2024

Runtime Calibration as State-Trajectory Feedback Control in Quantum-Classical Workflows Xiaolong Deng · 2026

Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations Arthur Fyon, Julien Brandoit, Loris Mendolia, Damien Ernst, Jean-Michel Redouté, Guillaume Drion · 2026

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA Michelangelo Barocci, Vittorio Fra, Enrico Macii, Gianvito Urgese · 2026

Enhancing Instruction Prefetching via Cache and TLB Management Alexandre Valentin Jamet, Georgios Vavouliotis, Marti Torrents, Dimitrios Chasapis, Marc Casas · 2026

Hardware Design Using Verilog Daniel Page · 2009

MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems Zhuoshan Zhou, Chen Zhang, Shuyi Zhang, Qijun Zhang, Haibo Wang, Zhe Zhou, Zhipeng Tu, Guangyu Sun, Yijia Diao, Zhigang Ji, Jingwen Leng, Guanghui He, Minyi Guo · 2026

LLM-Driven Design Space Exploration of FPGA-based Accelerators Vinamra Sharma, Xingjian Fu, Jude Haris, José Cano · 2026

A virtually connected probabilistic computer as a solver for higher-order, densely connected, or reconfigurable combinatorial optimisation problems Amy J. Searle, Harry Youel, Fredrik Hasselgren, Annika Möslein, Ramy Aboushelbaya, Marko von der Leyen · 2026

XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA Feng Yu, Hongshi Tan, Yao Chen, Weng-Fai Wong, Bingsheng He · 2026

Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture Masashi Masuda, Abderazek Ben Abdallah, Arquimedes Canedo · 2009

Analysis of Hardware Sorting Units in Processor Design Carmelo C. Furlan · 2024

Principles of Secure Processor Architecture Design Jakub Szefer · 2019

Processor Design Case Studies · 2001

Vector and Multiple-Processor Machines · 2001

Principles of Secure Processor Architecture Design Jakub Szefer · 2019

Processor Design Case Studies · 2017

An Integrated PPG and ECG Signal Processing Hardware Architecture Design of EEMD Processor Wai-Chi Fang, I-Wei Chen · 2019

Processor and Instruction Set Architectures · 2007

Hardware Cost Estimation for Application-Specific Processor Design Teemu Pitkänen, Tommi Rantanen, Andrea Cilio, Jarmo Takala · 2005

RFAmpDesigner: A Self-Evolving Multi-Agent LLM Framework for Automated Radio Frequency Amplifier Design Hang Lu, Guochang Li, Qianyu Chen, Huiyan Gao, Shaogang Wang, Xuanyu He, Yiwei Liu, Gaopeng Chen, Nayu Li, Xiaokang Qi, Chunyi Song, Zhiwei Xu · 2026

Arcane: An Assertion Reduction Framework through Semantic Clustering and MCTS-Guided Rule Exploring Hongqin Lyu, Yonghao Wang, Zhiteng Chao, Tiancheng Wang, Huawei Li · 2026

Towards an End-To-End System for Real-Time Gesture Recognition from Surface Vibrations Florian Hettstedt, Cedric Giese, Tianheng Ling, Keiichi Yasumoto, Gregor Schiele, Andreas Erbslöh · 2026

ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits Lukas Sekanina, Vojtech Mrazek · 2026

Establishing Robust Retinal Eye Tracking: A Weakly Supervised Algorithmic Framework Bo Wen, Dillon Lohr, Yatong An, Pushkar Anand, Alexander Fix, Ruobing Qian, Catherine A. Fromm, Yimin Ding, Truong Nguyen, Mohamed El-Haddad, Francesco La Rocca · 2026

Scaling Qubit Mapping and Routing With Position Graph Abstraction and Memoization Brent Russon, Bao Bach, Ed Younis, Ilya Safro · 2026

A Hybrid Classical-Quantum Annealing Algorithm for the TSP Siwei Hu, Victor Lopata, Salvatore Sinno, Shruthi Thuravakkath, Paolo Zuliani · 2026

SCOPE: Siamese Contrastive Operon Pair Embeddings for Functional Sequence Representation and Classification Akarsh Gupta, Kenneth Rodrigues, Sagnik Chatterjee · 2026

Basic Computer Security Concepts Jakub Szefer · 2019

A model-year architecture approach to hardware reuse in digital signal processor system design J. Wedgwood, G. Buchanan · 2024

Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation Kieran Carrigg, Sigur de Vries, Amirhossein Sadough, Marcel van Gerven · 2026

Time Domain Near Memory Computing Engine Sarthak Antal, Steve Enosh · 2026

A Hardware-Aware, Per-Layer Methodology for Post-Training Quantization of Large Language Models Earl Killian · 2026

Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation Gabriel Fernandes Thomaz, Jerusa Marchi, Eduarda Rodrigues Monteiro, Fernando Augusto Caletti de Barros, Evandro Chagas Ribeiro da Rosa · 2026

Fine-granularity 3D Processor Design Yuan Xie, Jishen Zhao · 2015

Hardware Description Languages Sarah L. Harris, David Harris · 2022

General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies N. Venkateswaran, C. Chandramouli · 2003

Session 2B: Application Specific Memory and Processor Architecture Design Techniques · 2004

A generic wrapper architecture for multi-processor SoC cosimulation and design Sungjoo Yoo, G. Nicolescu, D. Lyonnard, A. Baghdadi, A.A. Jerraya · 2024

Conclusions and Future Work Vahid Lari · 2016

Hardware / Software Co-design using LEON3 Processor: AES as Case Study Priti S.Chimankar, Meghana A. Hasamnis, S. S. Limaye · 2012

Hardware: The ERRIC Architecture Igor Schagaev, Eugene Zouev, Kaegi Thomas · 2019

Wireless sensor nodes processor architecture and design Ali El Kateeb, Aiyappa Ramesh, L. Azzawi · 2008

Improved Processor Design Project Testing Ryan Lund, Connor McMahon, Dan Garcia, Borivoje Nikolic · 2021

A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware Gerardo Orlando, Christof Paar · 2001